| Starts: | Wednesday August 26, 2009 at 5:30pm |
|---|---|
| Ends: | Wednesday August 26, 2009 at 8:00pm |
| Event Type: | Training/Seminar |
| Region: | San Francisco Bay Area |
| Location: |
Juniper Networks 1220 N Mathilda Ave Sunnyvale, CA 94089 US |
| Price: | |
| Website: | http://www.fpgacentral.com/fpgacamp |
| Industry: | semiconductors |
| Keywords: | Fpga, Cpld, Pc Ie, Interlaken, Xaui |
| Intended For: | FPGA Designers & Managers |
| Organization: |
THE EVENT IS FULL.
If you RSVP now you will be in our waiting list (unfortunately linkedin does not allow us to close the event.)
The idea behind FPGA Camp is to bring engineers together and discuss FPGA, mainly NextGen FPGA technology, application, methodology, best practices and challenges. Also provide a location to meet other local FPGA designers to share their stories.
We are hoping that this would act as a platform to bring all the FPGA users together more often.
Agenda:
5:30 - 6:00 : Registration and demo
6:00 - 7:00 : Tech Talk- "High Speed Serial Interface: Protocols, IPs & Devices"
7:00 - 7:30 : Vendor talk- a brief talks from the vendors offering High Speed Serial Interface devices or IPs. (5 to 10 Mns each).
7:30 - 8:00 : Networking and exhibits
High Speed Serial Interface: Protocols, IPs & Devices
Recent expansion in the video usage and growth in the Internet use have created a demand to move more data faster than ever. To meet this demand, system & chip designers are moving towards high speed serial interfaces such as PCIe, XAUI, Interlaken, XFI, 10GbE etc.
With FPGA devices currently supporting speeds upto ~12.5Gb per IO pair, which makes FPGAs a unique choice for the next design.
This talk will focus on familiarizing people with various protocols (both currently used & emerging), IPs & Devices which can be used to solve the next system problem.
The talk will be followed by quick presentations from some of the vendors offering these solutions (no marketing talk, only technical).
Registration: FREE, Send us a email at fpgacamp@fpgacentral.com to RSVP for the event or RSVP here at LinkedIN.
There is NO ENTRY FEE for users or vendors. Feel free to bring a friend.
Contact us if you would like to: * Volunteer with us * Speak or Refer a speaker * If you are a vendor - Would like to put a booth - Free - Demo/Talk about a product (Tell us what and why)- Free
1st ever FPGA Camp, hope to start a good trend
Would love to attend this event. I look forward to watching webcasts of it. Good luck, Mr. Singh!
Great, looking forward to attending this event
I'd like to volunteer. Let me know what you need. Also, if you need sodas/water, I can bring them ... maybe a sponsors plug for ASICSoft :-) Mike 408-998-2800 x11
What a great idea! Tweeted it! http://twitter.com/signalintegrity
With today's designs implementing high speed SERDES (~10Gbps), DDR2/DDR3, higher board layer counts, higher operating frequencies, and more number of voltage rails there is a need to do Signal and Power Integrity on the board to look at crosstalks, EMI, heat, and Power Distribution Network implementations. Register for the seminar to learn more http://www.mentor.com/products/pcb-system-design/events/green-systems-design-hyperlynx-si-seminar
Would love to attend. Please add me in. Thanks. Victor Shadan
When is the next meeting?
New FPGA Camp announced for Nov'11, 2009 http://events.linkedin.com/FPGACamp-Debugging-FPGA/pub/136177