FPGACamp - Debugging Your FPGA

Starts: Wednesday November 11, 2009 at 5:00pm
Ends: Wednesday November 11, 2009 at 8:30pm
Event Type: Conference
Region: San Francisco Bay Area
Location: 5301 Stevens Creek Blvd
Santa Clara, CA 95051 US
Price: FREE
Website: http://www.fpgacentral.com/fpgacamp
Industry: semiconductors
Keywords: Fpga, Semiconductor, Vlsi, Verification, Verilog, Serdes, Signal Integrity, Electronics, Simulation, Chip Design, Xilinx, Altera, Lattice
Intended For: engineer, hardware engineer, design engineer, verification engineer, signal integrity, fpga designer, fpga engineer
Organization: FPGA Central

To register just RSVP here & yes Dinner will be provided so bring a friend !!

There are two distinct phases in bringing an FPGA system to market: the design phase and the debug and verification phase. The primary tasks in the design phase are entry, simulation, and implementation. The primary tasks in the Debug and Verification phase are to validate the design and correct any bugs found.

The recent advancements in FPGA densities have changed the way we think of design & debug of a FPGA. This camp will focus on what can you do as an engineer to make debugging your FPGA a science rather then an art. It will also introduce to you various tools that you can use to shorten the debug cycle.

Agenda:

5:00 PM- 6:00 PM: Registration and exhibits (booths from various vendors) 6:00 PM - 6:05 PM: Introductions - Vikash Rungta 6:05 PM - 8:30 PM: Tech Talk 8:30 PM- 9:00 PM: Networking and exhibits (booths from various vendors)

Tech talk from: * Eric Bogatin, BeTheSignal.com - How the board will screw up your beautiful transceiver signals, and what you can do about it * Sid Khattar, eInfoChip - Design and Validation Techniques for FPGA Debug * Chris Schalick, Gaterocket - Debugging FPGA designs may be harder than you expect * Mike Peattie & Vinay Singh, Xilinx - Improving Productivity in FPGA Debug and Verification * Richard Wilson, Altium - Using FPGAs to embed test instruments into your PCB design * Gordon Getty, Agilent - Using Logic Analyzers, Scopes and other tools to debug your FPGA

Registration: FREE! Feel free to bring a friend. Just RSVP here or fill the form at http://www.fpgacentral.com/fpgacamp/silicon-valley-ca-usa/debugging-your-fpga-11-nov-2009-silicon-

Contact us if you would like to:

  • Volunteer with us
  • Speak or Refer a speaker
  • If you are a vendor
  • Would like to put a booth - Free
  • Demo/Talk about a product (Tell us what and why)- Free ( http://www.fpgacentral.com/fpgacamp/guideline )
  • Buy audience some food / drinks
  • Give away eval boards, books, kits or goodies to attendees

IF YOU WOULD LIKE US TO SEND EVENT REMINDER ALSO SIGN UP AT http://www.fpgacentral.com/fpgacamp or join LinkedIn FPGA Group: http://www.linkedin.com/e/gis/54049/5B3F2217B20B

Comments (3)

  • please do conduct the similar event in bangalore as well. if you are conducting, please intimate us.

    When
    Posted about 1 month ago
    Author
    mahesh penugonda, Module Lead at MindTree Ltd.
    Quotes
  • Attending

    When
    Posted 19 days ago
    Author
    Sanjay Thatte, Technical Marketing Manager at Mentor Graphics
    Quotes
  • Event is tomorrow. Please register today (last day)

    When
    Posted 13 days ago
    Author
    Vikram Singh, Manager at Lamingo
    Quotes