| Starts: | Thursday November 05, 2009 at 9:00am |
|---|---|
| Ends: | Thursday November 05, 2009 at 5:00pm |
| Event Type: | Conference |
| Region: | San Francisco Bay Area |
| Location: |
Sun Conference Center at Agnews Historic Park 4030 George Sellon Cir Santa Clara, CA 95054 US |
| Price: | |
| Website: | http://www.synopsys.com/Community/Interoperability/Pages/InteropForumNov09.aspx |
| Industry: | semiconductors |
| Keywords: | Eda, Interoperability, Edac, Vmm, Sun Microsystems, Accellera, Ipl Alliance, P Cell, Si2, Open Access, Ma Pin, Tlm 2.0, Osci, System C, Synopsys, System Verilog, Verification, Standards, Low Power, Ieee |
| Intended For: | EDA vendors, Chip Designers, Verification Engineers, Electronic Engineers, CAD Engineers, CAD Managers |
| Organization: |
This Forum provides EDA vendors and their customers an opportunity to exchange information and ideas on EDA tool interoperability including information on new interface technologies, future enhancements, upcoming news, and successes from developers and customers.
Registration is absolutely FREE.
The first 10 attendees who sign in on the morning of the event will receive a $15 Starbucks gift card.
The first 100 attendees will receive a copy of the Verification Methodology Manual for Low Power (VMM-LP) and Doulos’ VMM Golden Reference Guide Primer.
Lunch and a light breakfast are included.